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Publication Detail
A 14-mW, 153.6-MHz clock-rate Δ∑ modulator for WCDMA with 77-dB SFDR using constant resistance CMOS input sampling switch
Abstract
The performance of a switched-capacitor delta-sigma (DeltaSigma) analog-to-digital converter (ADC) is greatly degraded by the linearity of the input sampling switch. This is especially so in older cheaper technologies where very-low threshold voltage devices are unavailable. To address the input switch sampling distortion issue, the use of an optimized bootstrapped CMOS switch is proposed in this paper, featuring a constant on- resistance over the entire input signal range. The dynamic range improvement with the proposed approach is validated with the design of a fourth-order, switched-capacitor DeltaSigma modulator for WCDMA in a 0.35-mum BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 77 dB is achieved at a clock-rate of 153.6 MHz. The modulator dissipates 14 mW from a 2.7-V power supply and occupies an area of 0.2 mm2.
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Dept of Electronic & Electrical Eng
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