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Publication Detail
A high-speed scalable CMOS current-mode winner-take-all network
  • Publication Type:
  • Authors:
    Demosthenous A, Taylor J, Smedley S
  • Publisher:
  • Publication date:
  • Place of publication:
    Berlin / Heidelberg, Germany
  • Pagination:
    371, 376
  • Published proceedings:
    Artificial Neural Networks - ICANN 96: 1996 International Conference Bochum, Germany, July 16–19, 1996: Proceedings
  • Volume:
  • Series:
    Lecture Notes in Computer Science
  • Editors:
    Malsburg CVD,Seelen WV,Vorbrüggen JC,Sendhoff B
  • ISBN-13:
  • Status:
  • Language:
A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. Simulations show that the new circuit can resolve input currents differing by less than 1mgrA with a negligible loss of operating speed. Detailed simulations and preliminary measured results of a single WTA cell and of a complete 8-input tree WTA network are presented.
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