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Publication Detail
A CMOS low-power ADC for DVB-T and DVB-H systems
  • Publication Type:
  • Authors:
    Adeniran OA, Demosthenous A, Clifton C, Atungsiri S, Soin RS
  • Publisher:
    IEEE Computer Society
  • Publication date:
  • Place of publication:
    Piscataway, US
  • Pagination:
    209, 212
  • Published proceedings:
    2004 IEEE International Symposium on Circuits and Systems: Proceedings: May 23-26, 2004, Sheraton Vancouver Wall Centre Hotel, Vancouver, British Columbia, Canada
  • Volume:
  • ISBN-10:
  • Status:
  • Language:
This paper describes the design of a 10-bit, 25MS/s analogue-to-digital converter (ADC) suitable for digital video broadcasting over terrestrial (DVB-T) and handheld (DVB-H) systems. The ADC is based on a 4-3-3-stage pipeline architecture and employs dynamic comparators and Miller-hold sample-and-hold amplifiers for high-speed operation and low-power consumption. Simulated results in a 0.35μm CMOS process show that the converter achieves 56dB signal-to-noise ratio(SNR) and 57dB spurious-free dynamic range (SFDR). The converter input range is 2V peak-to-peak differential and the total power consumption is 27mW from a 2.8V power supply.
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