UCL  IRIS
Institutional Research Information Service
UCL Logo
Please report any queries concerning the funding data grouped in the sections named "Externally Awarded" or "Internally Disbursed" (shown on the profile page) to your Research Finance Administrator. Your can find your Research Finance Administrator at http://www.ucl.ac.uk/finance/research/post_award/post_award_contacts.php by entering your department
Please report any queries concerning the student data shown on the profile page to:

Email: portico-services@ucl.ac.uk

Help Desk: http://www.ucl.ac.uk/ras/portico/helpdesk
Publication Detail
A segmented analog calibration scheme for low-power multi-bit pipeline ADCs
Abstract
A segmented background calibration scheme for low-power, high-resolution (>10-bit) multi-bit pipeline analog-to-digital converters (ADCs) is described. The technique uses a low-bandwidth, high-precision DeltaSigma modulator for MDAC residue digitization, thus negating the need for an ultra-low offset analog comparator. Behavioral simulation results for 1% MDAC capacitor mismatch, show signal-to-noise-plus-distortion ratio (SNDR) improvement of 19 dB and spurious-free-dynamic-range (SFDR) improvement of 24 dB over an uncalibrated 12-bit ADC. The scheme has small digital and analog silicon area and power consumption overhead, thus making it suitable for low-power video-rate ADCs for mobile applications.
Publication data is maintained in RPS. Visit https://rps.ucl.ac.uk
 More search options
UCL Researchers
Author
Dept of Electronic & Electrical Eng
University College London - Gower Street - London - WC1E 6BT Tel:+44 (0)20 7679 2000

© UCL 1999–2011

Search by