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Publication Detail
A segmented analog calibration scheme for low-power multi-bit pipeline ADCs
A segmented background calibration scheme for low-power, high-resolution (>10-bit) multi-bit pipeline analog-to-digital converters (ADCs) is described. The technique uses a low-bandwidth, high-precision DeltaSigma modulator for MDAC residue digitization, thus negating the need for an ultra-low offset analog comparator. Behavioral simulation results for 1% MDAC capacitor mismatch, show signal-to-noise-plus-distortion ratio (SNDR) improvement of 19 dB and spurious-free-dynamic-range (SFDR) improvement of 24 dB over an uncalibrated 12-bit ADC. The scheme has small digital and analog silicon area and power consumption overhead, thus making it suitable for low-power video-rate ADCs for mobile applications.
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