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Publication Detail
A generic multi-modulus divider architecture for fractional-N frequency synthesisers
  • Publication Type:
    Conference
  • Authors:
    Wang H, Brennan PV, Jiang D
  • Publisher:
    IEEE Computer Society
  • Publication date:
    2007
  • Place of publication:
    Piscataway, US
  • Pagination:
    261, 265
  • Published proceedings:
    IEEE International Frequency Control Symposium, 2007: Joint with the 21st European Frequency and Time Forum
  • ISBN-13:
    9781424406470
  • Status:
    Published
  • Language:
    English
  • Keywords:
    PLL, fractional-N, synthesiser
  • Notes:
    Symposium took place between 29 May-1 June 2007 at Geneva International Conference Center, Switzerland
Abstract
This paper describes the design of a new technique and architecture of multi-modulus divider for Sigma-Delta fractional-N PLL frequency synthesisers. The proposed architecture uses a memory-controlled technique that can achieve a wider range of prescaler modulus values, more flexible operation, and lower power dissipation. It has been implemented in an FPGA in conjunction the store-sequence architecture and a range of Sigma-Delta modulators. Both simulated and measured results are shown to demonstrate that a substantial improvement in performance is possible.
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