Institutional Research Information Service
UCL Logo
Please report any queries concerning the funding data grouped in the sections named "Externally Awarded" or "Internally Disbursed" (shown on the profile page) to your Research Finance Administrator. Your can find your Research Finance Administrator at https://www.ucl.ac.uk/finance/research/rs-contacts.php by entering your department
Please report any queries concerning the student data shown on the profile page to:

Email: portico-services@ucl.ac.uk

Help Desk: http://www.ucl.ac.uk/ras/portico/helpdesk
Publication Detail
CBSC-based pipelined analog-to-digital converters: Power dissipation bound analysis
The comparator-based switched-capacitor (CBSC) technique has been used in low power analog-to-digital converters (ADCs). The objective of this paper is to derive the theoretical minimum power dissipation bound for CBSC-based pipelined ADCs with digital error correction of 1.5 bit/stage. To achieve this, the constituent building blocks whose performance is limited by noise, are examined. The optimum values of the design parameters influencing the power dissipation bound are also investigated including the optimal output ramp rates needed to achieve a given linearity constraint, comparator bias current and delay time. The derived equations are verified through behavioral simulation in MATLAB. © 2012 IEEE.
Publication data is maintained in RPS. Visit https://rps.ucl.ac.uk
 More search options
UCL Researchers
Dept of Electronic & Electrical Eng
Dept of Electronic & Electrical Eng
University College London - Gower Street - London - WC1E 6BT Tel:+44 (0)20 7679 2000

© UCL 1999–2011

Search by