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Publication Detail
FPGA-based bit-error-rate tester for SEU-hardened optical links
  • Publication Type:
    Conference
  • Authors:
    Detraz S, Silva S, Moreira P, Papadopoulos S, Papakonstantinou I, Seif El Nasr S, Sigaud C, Soos C, Stejskal P, Troska J, Versmissen H
  • Publication date:
    01/12/2009
  • Pagination:
    636, 640
  • Published proceedings:
    Proceedings of the Topical Workshop on Electronics for Particle Physics, TWEPP 2009
  • ISBN-13:
    9789290833352
  • Status:
    Published
Abstract
The next generation of optical links for future High-Energy Physics experiments will require components qualified for use in radiation-hard environments. To cope with radiation induced single-event upsets, the physical layer protocol will include Forward Error Correction (FEC). Bit-Error-Rate (BER) testing is a widely used method to characterize digital transmission systems. In order to measure the BER with and without the proposed FEC, simultaneously on several devices, a multi-channel BER tester has been developed. This paper describes the architecture of the tester, its implementation in a Xilinx Virtex-5 FPGA device and discusses the experimental results.
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